Field of the Disclosure
The present disclosure relates generally to an apparatus for an integrated clock gating cell (ICG), and more particularly, to an apparatus for a low power, high speed integrated clock gating cell.
Description of the Related Art
An integrated clock gating cell (ICG) reduces power consumption in circuits that use a clock signal by propagating (i.e., enabling) the clock signal only when it is required by a circuit. An ICG may be implemented using a static complementary metal oxide semiconductor (CMOS) design technique, which includes p-channel MOS (PMOS) transistors and n-channel MOS (NMOS) transistors.
A dynamic version of an ICG was introduced to improve (i.e., reduce) the setup time of the ICG.
In a dynamic logic gate, when a clock signal is low (e.g., 0 volts), a PMOS transistor is turned on to precharge an output node of the logic gate to a high voltage (e.g., a supply voltage VDD) before it is determined (e.g., evaluated) what the output of the logic gate should be, based on the inputs to the logic gate.
When the clock signal is high (e.g., VDD), the PMOS transistor is turned off and an NMOS transistor is turned on to evaluate what the output of the logic gate should be. That is, it is determined whether the output node should either be discharged to a low voltage (e.g., 0 volts) if the output of the logic gate should be low or left alone to retain the precharged voltage if the output of the logic gate should be high.
Since the precharged voltage is susceptible to being lost due to leakage or accidental discharge, a static logic gate may be used after each dynamic stage to ensure retention of the logic value. Such a design is commonly referred to as Domino logic, because the stages are evaluated one at a time, in order, like falling dominoes.
A drawback of a dynamic ICG of the related art is that precharging is performed each time a clock signal goes low, resulting in power being consumed, even when the clock signal is not propagated (i.e., not enabled).
Another drawback of a dynamic ICG of the related art is that the ICG uses both a clock signal and an inverted version of the clock signal to propagate enabled data to a static stage.
An inverted clock consumes power costs, because it switches the clock every time the non-inverted clock signal switches.